ASIC Static Timing and Synthesis Engineers (00005)

Client: Northrop Grumman

Position: ASIC Static Timing and Synthesis Engineers (00005)

Work Location: Baltimore, MD

Duration: Long term contract (a year+) or CTH (NG will offer FT opportunity after a year for the right candidate, if candidate is interested) 

Clearance: Active Secret (No interim or inactive)

Job Description:

STA (Static Timing Analysis) Design Engineer

- looking for experienced Timing Analysis & Sign-off expert for complex digital design. The engineer will be responsible for owning & working with team on constraint development, timing closure using latest nanometer technologies

Responsibilities

- Work with systems architect/IP experts to develop level timing constraints

- Work with physical design team on design constraint and timing closure

- Be hands-on technical individual contributor

Requirements

- secret government clearance within last 5 years

- good knowledge of EDA tools and scripting

- BSEE with 8 years of experience or MSEE with 5 years’ experience in static timing & RTL Design

- Must be a very good team player with a very good oral, written and interpersonal communication skills

Tool experience

- Synopsys Primetime-SI, Synopsys Design Compiler, Cadence Encounter Timing system

- Scripting languages – tcl, csh, perl, Makefile

- Operating systems: linux, window

- Revision control: SVN, git

Desirable

- Experience with RTL synthesis

- Digital simulation, formal verification, linting, test insertion & atpg generation

- Experience with ARM CPUs, peripherals such as I2C, SPI, UART, Asynchronous interface designs, peripherals and interconnect protocols such as AHB, AXI, PCIE etc

- Tool experience – Mentor Questa, Mentor Tessent, Synopsys Formality

Keywords

- STA, SSTA, OCV, Margins, Derates, Sign-off derate, PTV variation, sign-off criteria, STA methodology, sign-off methodology, binning

• secret government clearance within last 5 years\

• looking for experienced Timing Analysis & Sign-off expert for complex digital design. The engineer will be responsible for owning & working with team on constraint development, timing closure using latest nanometer technologies

All your information will be kept confidential according to EEO guidelines.