We are looking for multiple Senior Design Engineers, at all levels from Senior Engineer to Senior Principal Engineer. You will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile standards, giving complete coverage to the entire globe. AccelerComm develops the baseband signal processing technology, using hardware acceleration to generate world-leading error resilience, capacity and power efficiency.
You will work on the latest generation space-qualified devices, delivering standalone IP and integrated IP solutions.
AccelerComm will NOT sponsor H1 visa nor practical training.
As a Senior Hardware Design Engineer, you will be responsible for:
Designing micro-architectures and RTL implementations to meet the requirements provided by Algorithm and System Architecture teams. Providing feedback to Algorithm and System Architecture teams to improve efficiency of RTL designs
Implementing designs targeting FPGA and/or ASIC using industry standard techniques, design flows and tools, including the creation of appropriate block level and system level testbenches
Deploying your designs onto the latest FPGA development platforms for validation and system integration
Actively engaging with and adhering to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product
Essential:
- Expert knowledge of Verilog and SystemVerilog for complex ASIC/FPGA products
- Minimum 5 years of experience in industry, designing and delivering successful FPGA/ASIC designs implementing multiple Gbps high-speed data communication and connectivity protocols or baseband processing
- A strong skillset in delivering digital designs in the ASIC and FPGA industry
- A strong work ethic and focus on completing designs on time to meet customer delivery schedules
- Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
- Track record in collaborating across teams to produce integrated solutions
- Experience in technical documentation writing – design specifications, user guides, verification plans
- Expert user of EDA tools for simulation and synthesis
Desirable:
- Knowledge of 3GPP L1 and digital communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
- Familiarity with the AMBA/AXI bus protocols
- Understanding of UVM verification techniques or practical experience using UVM for IP verification
- Experience using C++/SystemC for design modelling and integration
- Experience with high speed interfaces such as PCI-E or JESD
- Knowledge of a scripting language, such as Python
- Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability
- Experience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools
We offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to stock options and a range of good quality company benefits including 401K, health/dental/optical insurance. We operate flexible working hours and offer hybrid working.
