Senior Engineer, Digital Design Engineering

Responsibilities

This position will involve many of the following tasks. 

• FPGA prototyping of design

• Development of models & self checking mechanisms for FPGA

• HW & S/W Codesign

• Architectural design and specification of blocks.

• Verilog/SystemVerilog RTL design

• Interaction with customer and stakeholders

• Design to meet timing, area, low-power, DFT, manufacturing test and timing targets for market

• All aspects of design work including interaction with verification and analog team. 

• Interaction with implementation team to convert RTL to silicon. Defining timing constraints and performing static timing analysis

• Working with architecture and design teams to determine functionality protocols

Qualifications

Bachelor's or Master's degree, in Engineering (Electronic Engineering) or equivalent 

• Architectural design and specification of complex systems, especially in system on chip with processors. 

• Deep knowledge of FPGA development flow

• FPGA modelling

• Verilog/SystemVerilog RTL design - with emphasis on AHB, AXI protocols and processor architecture on ARM cores. 

• Design to meet timing, area, low-power, manufacturing test and timing targets for market. 

• All aspects of design work including interaction with verification and analog team. 

• Interaction with implementation team to convert RTL to silicon. 

• Working with architecture and design teams to determine functionality protocols 

• Ability to work well in a diverse team environment 

• Strong interpersonal, teamwork and communication skills are required. 

• Precise documentation and attention to detail are essential. 

• Quick to adopt new technologies

• Ability to work well in a diverse team environment 

• Strong interpersonal, teamwork and communication skills are required. 

• Be self-motivated and enthusiastic. 

• Good problem solving skills. 

• Architected design and specification of blocks and platforms. 

• Act as design hub to interact with stakeholders – test, application, physical implementation, verification 

• Design to meet area, low-power, manufacturing test and timing targets. 

• Intellectual Property (IP) block design and integration. 

• Perform timing, power and CDC analysis on design 

• Verification of blocks using UVM. 

• Mixed-signal integration and verification / co-simulation 

• Working with product development teams to align digital system architecture and methodologies with product roadmap