ASIC Physical Designers - IV

• CW will assist the Physical Design Team in executing RF and analog custom layout.
• Tasks include drawing the layout, running verification (LVS, DRC, ERC, etc.), debugging errors and providing clean designs to the design team for extraction simulations.
• Physical designers maintain organized hierarchy and clean database according to existing processes.
• 5 yrs custom RF and Analog Physical Design experience including calibre verification tools in the cadence design environment.
• Experience with Foundry 28nm technology
• Multiple GHz layout experience
• Cadence Virtuoso XL, Calibre verification an extraction.
• Unix
• Communication and team skills.
• BS – electrical engineering preferred.

All your information will be kept confidential according to EEO guidelines.