ASIC Design Verification Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

Responsibilities

THE ROLE:

As a member of the front-end verification team, you will help bring to life cutting-edge designs and work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.THE PERSON:

A successful candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. He/she will have a passion for modern, complex ASIC architecture, digital design, and verification in general.

KEY RESPONSIBILITIES:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Decide on verification and reuse strategy and testbench architecture
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Interact with project managers and system level DV teams to co-ordinate release schedules and feature staging
• Build the directed and random verification tests
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

PREFERRED EXPERIENCE:

• Proficient in IP level ASIC verification strategies
• Proficient in debugging RTL code using simulation tools
• Expert in the UVM concepts and SystemVerilog language
• Proficient in architecting UVM testbenches and working in Linux and Windows environments
• Experienced in developing UVM based verification frameworks and testbenches, processes and flows
• Comfortable automating workflows in a distributed compute environment.
• Exposure to simulation profile, efficiency improvement, acceleration, formal verification
• Scripting language experience: Perl, Python, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset
• Prior exposure to networking protocols such as Ethernet, UAL, LLR, CBFC is desired
• Experienced in using AI tools

ACADEMIC CREDENTIALS:  

Bachelors or Masters degree in Computer Engineering/Electrical Engineering or Computer Science

#LI-JG1

#Hybrid

Qualifications

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.