Design Verification Engineer (Intern 2026)

Join Astera Lab’s ASIC team as Design Verification Co-Op working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will be passionate about silicon engineering with a background in VLSI and/or computer architecture. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools.

Basic qualifications:

• Completed 3rdyear of study, minimum GPA: 3.5
• Strong academics and technical background in either Computer Engineering or Electrical/Electronic Engineering.
• Authorized to work in Canada and start immediately.

Required experience:

• Courses/Projects in digital logic, programming languages, computer architecture.
• Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog.
• Familiarity with any of the scripting languages Python, Perl, etc. and hands-on experience in C/C++.
• Detailed oriented with strong analytics and debugging skills.

Preferred experience:

• Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes.
• Knowledge of communication interfaces like SPI, I2C, JTAG.
• Courses in digital communications and computer networks.
• System Verilog test bench(UVM)
• Familiarity with Synopsys EDA tools.