Senior RTL Design Engineer

Responsibilities: 
• Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.
• Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
• Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.
• Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
• Collaborate with performance modelling team for performance exploration and optimization to meet performance goals.

Requirements: 

 • 8+ yrs of recent industry experience in high-performance, energy-efficient CPU designs.
• Expertise in CPU processor designs in one or more of the following areas: instruction fetch and decode; branch prediction; register renaming and instruction scheduling; scalar and/or vector execution units; load-store unit; cache and memory subsystems.
• Knowledge of RISC-V architecture is a plus.
• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Experience with Scala and/or Chisel is a plus.
• Attention to detail and a focus on high-quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Knowledge of at least one object-oriented and/or functional programming language.
• Background of successful CPU development from architecture through tapeout.

 • MS/ PhD degree in EE, CE, CS or a related technical discipline, or equivalent experience.

#LI-DNI