DFT Engineer

Role and Responsibilities

• Implement scan architecture and perform scan insertion and stitching at RTL and gate level, using the Siemens Tessent flow.
• Generate ATPG patterns (stuck-at, transition) and achieve the target test coverage.
• Run pattern simulation and debug failures, including mismatches in zero-delay and timing-annotated simulations.
• Verify JTAG (TAP controller, instructions and test data registers) and scan modes at RTL and gate-level simulation (GLS).
• Run DFT rule checks (DRC) and resolve violations with the design team.
• Work with the RTL, physical design and verification teams to close DFT requirements and meet timing for scan and test modes.
• Support DFT signoff checks and release of test patterns for tape-out.
• Document the DFT architecture, test modes and verification results.

Requirements

• 2 years of experience in scan implementation, verification and debug
• Hands-on experience in scan stitching, pattern generation and simulation
• Working knowledge of the Siemens Tessent flow for RTL DFT insertion and ATPG
• Experience in JTAG and scan verification at RTL and GLS