CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is simple: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.
Role and Responsibilities
- Be the primary point of contact for SoC program execution, and own the end-to-end plan from concept to release to manufacturing: architecture, IP, RTL, verification, physical design, DFT, tapeout, bring-up, validation, qualification and sampling.
- Build the integrated plan across SoC and chiplet/multi-die design, hardware, firmware, software, foundry, packaging, test and QA.
- Set milestones, phase gates and the critical path (spec freeze, RTL freeze, netlist and timing signoff, tapeout readiness) with engineering leads, and own the gate reviews.
- Front-end: Drive RTL milestones and the RTL change-control process, track lint/CDC/RDC and DFT closure, and own verification closure (coverage, regression health, bug burn-down).
- Physical design: Drive floorplan, bump map, timing and power convergence, IR/EM and signoff, and coordinate netlist, constraint, IP-view and package handoffs across FE, PD, analog and packaging.
- Emulation: Own the emulation and FPGA prototyping plan, and make sure results feed back into RTL and firmware before tapeout.
- SW interfacing: Keep hardware and software aligned on register map, memory map, boot flow and driver/firmware interfaces, and track SW readiness for bring-up.
- Dependencies: Maintain a cross-team dependency tracker with owners and dates, resolve blockers, and escalate with options and a recommendation.
- Manage IP vendors (SerDes, PCIe/Ethernet/UCIe, processor cores, PHYs), the foundry and OSAT partners, holding them to delivery and quality commitments.
- Manage scope, schedule, budget, MPW/mask and resource plans, and drive decisions when they change.
- Identify technical and schedule risks early (IP maturity, timing, power, area, package co-design, test coverage), drive mitigation, and escalate.
- Define program health metrics and build the executive dashboards (bug burn-down, coverage, timing and power convergence, bring-up status).
- Own sample readiness and release-to-manufacturing criteria with engineering and operations, including ATE test, yield and silicon characterization.
- Run the program cadence across global sites and establish program management processes and tools as CScale moves into production.
Skills and Knowledge
- Strong technical program management: integrated scheduling, critical path ownership, driving issues to closure.
- Working knowledge of the full SoC flow: architecture, IP integration, RTL, verification (UVM, formal, emulation), physical design, STA, DFT, tapeout, post-silicon validation and qualification.
- Enough technical depth to engage engineers on PPA, IP configuration, clocking/reset, power domains and package co-design tradeoffs.
- Familiarity with emulation platforms, firmware/software bring-up, and high-speed interfaces (PCIe, Ethernet, UCIe, SerDes).
- Leads matrixed teams through influence, decides well with incomplete information, and communicates clearly with engineers and executives.
- Proficient with scheduling and tracking tools (MS Project, Jira, Notion).
- Bonus: reliability qualification (JEDEC/AEC), production test, yield ramp.
Required Experience
- 12+ years in semiconductor product development, including 7+ years leading SoC/ASIC programs, with earlier hands-on engineering experience.
- Has driven multiple SoC programs from concept through tapeout and release to manufacturing, ideally on advanced nodes.
- Experience managing IP vendors, foundries and OSAT partners, and leading programs across global teams.
- Startup or first-generation product experience.
- B.Sc. or higher in EE, Computer Engineering, Physics or a related field.
- Bonus: chiplet/multi-die and advanced packaging (2.5D/3D), silicon photonics or optical engine programs, high-speed connectivity products.
