Physical Design Engineer

You will be part of a Physical Design team for projects with GHz freq range and cutting edge technologies.

You will be responsible for Physical Design at Full Chip or block level in technologies of 28nm/14nm.

You will be responsible for Synthesis to PnR and Physical Verification closure of SoC/sub-chips.

Desired Skills and Experience:

· B. Tech. / M. Tech. with 5-8 years of experience in Physical Design

· Handled Netlist to GDS II at block level for multiple tape outs

· Hands-on experience on technology nodes like 28nm, 20nm, 14nm, 10nm

· Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly experience with ICC, PTSI, Encounter, Nanoroute, Calibre, StarRC

· Hands-on experience in floorplanning, placement optimizations, CTS and routing

· Hands-on experience in block/top level signoff STA, physical verification(DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk)

· Exposure in physical implementation of timing/functional ECO’s

· Good knowledge of VLSI process and device characteristics

· TCL, perl scripting

· B. Tech. / M. Tech. with 5-8 years of experience in Physical Design

All your information will be kept confidential according to EEO guidelines.