ASIC Design Verification Manager, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of experience in people management.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with universal verification methodology (UVM), SystemVerilog, or other scripting languages such as Python, Perl, Shell, Bash, etc.
• Knowledge of general purpose operating systems such as Linux and Android.
• Familiarity with ARM Instruction Set Architecture.

About the job

As an ASIC Design Verification Manager for Google's TPU designs, you will lead a team and own the functional verification for key components by guiding the development of advanced infrastructure at the subchip, subsystem, and full-chip levels. This includes developing comprehensive test plans, writing diagnostic codes, and building monitors and checkers to ensure quality assurance.
Additionally, you will partner closely with front-end design, architecture, and performance teams. By analyzing coverage across multiple dimensions, you will help ensure architectural compliance, verify functional correctness, and guide your team to meet key performance goals.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Guide the functional verification team for portions of TPU designs, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing functional verification infrastructure across subchip, subsystem, and fullchip level environments.
• Define and guide advanced verification strategies, including the use of simulation, for bug hunt, formal verification for corner-case bugs and emulation for system validation.
• Partner with front-end design, architecture, and performance teams to help ensure architectural compliance and achievement of performance goals.
• Analyze coverage from various dimensions and develop monitors and checkers for quality assurance.