HIring for ASIC verification

Bengaluru, IndiaOn-SiteFull-timePosted 4w ago

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Job description

JD for ASIC verification engineers: 5-8 years: 2 positions

- Implement verification environment independently using high level verification languages like System Verilog

- OVM/UVM methodology based implementation

- Experience on Synopsys VCS/ Mentor Questa

- Understand and execute the existing verification flows and improve the framework
- Contribute to verification methodology development and implementation

Job Requirements

- Knowledge of FPGA design and development flow is a plus

BE/B Tech/ME/M Tech - Electronics

Job details are sourced from the employer's original posting.

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About the company

Happiest Minds Technologies

Happiest Minds enables Digital Transformation for enterprises and technology providers by delivering seamless customer experience, business efficiency and actionable insights through an integrated set of disruptive technologies: big data analytics, internet of things, mobility, cloud, security, unified communications, etc. Happiest Minds offers domain centric solutions, IPs in IT Services, Product Engineering, Infrastructure Management and Security. These services have applicability across industry sectors such as retail, CPG, e-commerce, banking, insurance, hi-tech, engineering R&D, manufacturing, automotive and travel/transportation/hospitality. As a Mindful IT Company, the focus is on Being Mindful and Doing Mindful which involves perceiving immersively, processing non-judgmentally and performing empathetically. 60 minutes in a week is committed towards inculcating a mindful approach within the organization, using a select set of tools and techniques. Headquartered in Bangalore, India, Happiest Minds has operations in the US, UK, The Netherlands, Australia, Middle East and Turkey. For More Information pls go through http://www.happiestminds.com

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Industry: IT Services
Open roles: 5