Design Engineer for RF Heterogeneous Integration

Design Engineer for RF Heterogeneous Integration
Is it you we’re looking for?
Imec USA’s Florida-based R&D Center is developing innovative packaging solutions for next generation RF (>100 GHz) and ultra high speed (>100 Gbps) systems. Applications for this technology range from AI data centers to space-based communications. The key innovation is RF heterogeneous integration of silicon and III-V chiplets on the same interconnect platform.

The focus of this role is to develop building blocks and prototypes to advance imec RF interposer technologies. The fun challenge is optimizing the high frequency performance requirements while maximizing manufacturability for diverse use cases.
We are seeking a motivated and talented design engineer to join our multidisciplinary team. In this position you will contribute to the co-design, simulation, and characterization of advanced CMOS and III-V devices heterogeneously integrated on silicon interposer with low dielectric loss redistribution layers.

This opportunity offers the unique opportunity to work with a full-stack cross-site development team integrated across Kissimmee, Florida, and Leuven, Belgium. In addition, you will work closely with external customers and partners on test vehicles and prototypes to advance this cutting-edge technology into the marketplace. We foster a collaborative, hands-on environment where initiative and innovation are encouraged.
Here’s what you’ll do:
Design ciruits and layout building blocks like phase shifters, frequency multipliers, power amplifiers or phased-locked loops that benefit from heterogeneous integration.
Use EM simulation to extract parasitic effects and apply these learnings to RF interposer-chiplet co-design
Tape-out advanced CMOS designs using Cadence tools.
Tape-out III-V designs using RF circuit design tools like Keysight ADS in conjunction with EM simulation tools like Ansys HFSS.
Co-design the interconnect between active chiplets and the RF interposer.
Perform design reviews and create technical documentation and reports.
Contribute to publications in international journals and conferences.
Key Qualifications
PhD or a Master’s degree with 3+ years of relevant job experience.
Proficiency in Cadence Virtuoso and associated tools required for CMOS chiplet tapeout.
Proficiency in Keysight ADS and Ansys HFSS.
Strong communication skills for internal and external collaboration.
Strong understanding of state-of-the-art high frequency (>100 GHz) or high speed (>100 Gbbs) chiplet designs.
Very good English language skills (written and spoken).
Self-driven, hands-on, and pragmatic with a can-do attitude.
Additional Qualifications
US persons (citizen or green card) are preferred
Some background in heterogeneous integration is desirable
Demonstrated experience taking a chip from tape-out through RF measurement is highly desirable
Design experience with semiconductor interconnect processes like wafer bumping and flip-chip bonding is desirable
About imec
Imec is a world-leading research and innovation hub in nanoelectronics and digital technologies.

We leverage our world-class infrastructure and global ecosystem of partners across diverse industries to enable groundbreaking innovation in application domains, including healthcare, smart cities, mobility, logistics, manufacturing, and energy.
This opportunity is based at our U.S. R&D design center, which focuses on the R&D of novel applications and innovative solutions with superconducting electronics.
At imec, we believe that talent grows technology, and technology grows talent.

Our informal and progressive working environment offers a range of possibilities to take the initiative and grow in responsibility.
This is imec, find your place in it.