Need knowledge of design for test (DFT) structures such as scan chains, scan compression and verification concepts for test coverage (ATPG). Be able to generate ATPG and analyze coverage results and how to extend or optimize them. Need to know how to run gate simulation for to verify scan patterns to demonstrate functionality.
Min Qualifications:
5 years experience in DFT in ASICs
10 years experience in DFT for large scale ASICs. Experience with Mentor
Graphics DFT tools.
All your information will be kept confidential according to EEO guidelines.
Job details are sourced from the employer's original posting.
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About Mirafra : Mirafra is software service base organization started in 2004. We are 500+ employees in India and 250+ In US Clear visibility to senior management which helps for constant professional growth