We are seeking a highly experienced leader to head SoC Implementation / Physical Design for advanced semiconductor products. This role will own end-to-end physical design execution across complex SoCs, driving delivery from RTL to silicon for cutting-edge technology nodes.
The ideal candidate combines deep technical expertise with strong organizational leadership, capable of managing large global teams and delivering high-quality silicon on aggressive schedules.
Key Responsibilities
1. End-to-End Physical Design Ownership
- Lead complete SoC physical design execution including floorplanning, synthesis, place & route, CTS, routing, STA, PDN, PDV and signoff.
- Drive timing, power, IR/EM, and physical verification closure to achieve tapeout readiness.
- Deliver optimized PPA (Power, Performance, Area) across complex designs.
- Aligns with internal expectations of implementing designs on silicon with optimal quality, PPA, and cost efficiency
2. Program & Execution Leadership
- Own planning, tracking, and execution of physical design programs from specification through tapeout.
- Manage risks, dependencies, and schedules across multi-site global teams.
- Drive cross-functional alignment across RTL, DFT, STA, verification, and packaging teams.
- Ensure delivery to aggressive project timelines and quality metrics.
3. Team Leadership & Organization Development
- Build and lead high-performing global physical design teams.
- Drive hiring, mentoring, and career development across technical leads and engineers.
- Establish execution discipline, review mechanisms, and performance tracking.
- Interface with senior leadership for status reporting, escalation, and decision-making.
4. Technical Strategy & Innovation
- Define and deploy next-generation physical design methodologies.
- Drive automation, flow optimization, and tool innovation.
- Lead adoption of advanced node technologies (5nm and beyond).
- Improve scalability, productivity, and design quality through methodology enhancements.
5. Cross-Functional & Ecosystem Engagement
- Collaborate with architecture, RTL, verification, and product teams to ensure design convergence.
- Interface with EDA vendors and IP providers for tool and flow optimization.
- Support post-silicon bring-up, yield improvement, and production ramp activities.
Core Technical Expertise
- Full RTL-to-GDSII implementation flow
- Floorplanning, synthesis, PNR, CTS, routing
- STA and signoff methodologies
- EM/IR, PDN design, signal integrity
- Physical verification (DRC/LVS/ERC)
- Advanced node implementation (≤ 16nm / 5nm)
- Low power design (UPF/CPF)
- System-level integration (package, IO, board)
These responsibilities reflect core physical design tasks such as floorplanning, PNR, STA, verification, and optimization defined in internal role descriptions
Required Qualifications
- Bachelor’s or Master’s in Electrical / Electronics Engineering or related field
- 17+ years of experience in ASIC / SoC physical design
- Proven experience leading large-scale SoC programs
- Strong knowledge of industry EDA tools (Synopsys, Cadence flows)
- Demonstrated success in advanced node implementations
- Strong leadership, communication, and stakeholder management skills
Preferred Qualifications
- Experience in automotive or high-reliability SoCs
- Expertise in PDN / EMIR / SI closure at chip-level
- Experience with global team leadership across geographies
- Exposure to AI-driven design methodologies and automation
More information about NXP in the United States...
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
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