This role focuses on the design, optimization, and physical implementation of column-level ADC circuits used in CMOS image sensors.
The engineer will work closely with cross-functional teams to enhance performance, silicon efficiency, and image quality while ensuring robust and scalable layout solutions.
Responsibilities
- Work on detailed column ADC circuit design, with a focus on column layout design. Collaborating with other column ADC designers to optimize column ADC’s performance with minimum silicon area.
- Cross products column ADC layout comparison and IP layout development and maintenance.
- Perform RCX extraction of column circuit, taking care of critical signals parasitic analysis, and propose optimized design to improve column ADC performance and image quality.
- Image sensor pixel array and column ADC supply analysis using Totem or other methodologies, including worst case P2P resistor extraction, and optimize chip floorplan and power routing.
- Study design rules for new processes and provide physical design guidelines to design team. Debug and develop Calibre svrf files when needed.
- SKILL script to improve productivity and design robustness.
- Other duties as assigned.
Requirements
- Must have experience/knowledge in analog circuits and semiconductor.
- Experience/knowledge in CMOS image sensor readout circuit design
- Experience/knowledge in image sensor and camera system is a plus
- Minimum of 6+ years of relevant experience
- MSEE or equivalent
Annual base salary for this role in California, US is expected to be between $130,600 - $170,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
EOE/Minorities/Females/Vet/Disability
