FPGA Engineer

%3Cp class=%22MsoNormal%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan lang=%22EN-US%22%3ERadware is a global leader of cyber security and application delivery solutions for physical, cloud, and software defined data centers.%3C/span%3E%3C/span%3E%3C/p%3E%3Cp class=%22MsoNormal%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan lang=%22EN-US%22%3EAt Radware, we live and breathe cybersecurity.

It is our passion. Each day, our international team works to earn the trust of more than 12,500 organizations around the globe. Keeping them safe is our mission. To that end, we go head-to-head with politically motivated hacktivists, dangerous nation-state threat actors and other notorious cyber attackers -these are not your average adversaries. Backed by nearly 30 years of experience, Radware is best known for its technical excellence and innovative network and application security solutions.

That is why it is so important that we build our team with bold and bright talent.%3C/span%3E%3C/span%3E%3C/p%3E%3Cp class=%22MsoNormal%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan lang=%22EN-US%22%3E%3Cstrong%3EWhat is the job%5C:%3C/strong%3E%3C/span%3E%3C/span%3E%3C/p%3E%3Cp class=%22MsoNormal%22%3E%3Cspan style=%22color%5C:black;font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3Ejoin our Hardware Development Team.

The FPGA Engineer will participate the design of a high speed and cutting-edge FPGA technology in Redware’s platforms executing a full process of FPGA design.%3C/span%3E%3C/span%3E%3C/p%3E %3Cp class=%22MsoNormal%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan lang=%22EN-US%22%3E%3Cstrong%3EWhat you need%5C:%3C/strong%3E%3C/span%3E%3C/span%3E%3C/p%3E%3Cul style=%22margin-top%5C:0cm;%22 type=%22disc%22%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l1 level1 lfo1;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EB.Sc. in Electrical Engineering, Computer Engineering or equivalent%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l1 level1 lfo1;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EAt least 3 years of experience of FPGA development preferably for communication systems%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l1 level1 lfo1;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EExcellent design standards and strong debug skills%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l1 level1 lfo1;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EStrong knowledge of synthesis, place and route and timing compliance%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l1 level1 lfo1;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EExperience with VHDL/Verilog logic design principles along with timing, area and power implications%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l1 level1 lfo1;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EExperience with creation of complex designs including coding and integration of 3rd party IPs%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l1 level1 lfo1;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EExperience with verification methodologies, RTL and gate-level simulation%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l1 level1 lfo1;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EExperience with lab debugging equipment such as oscilloscopes and logic analyzers%3C/span%3E%3C/span%3E%3C/li%3E%3C/ul%3E%3Cp class=%22MsoNormal%22 style=%22line-height%5C:150%;margin%5C:0cm 5.4pt;mso-layout-grid-align%5C:none;mso-pagination%5C:none;text-autospace%5C:none;%22%3E%26nbsp;%3C/p%3E%3Cp class=%22MsoNormal%22%3E%3Cspan style=%22background-color%5C:white;color%5C:black;font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan lang=%22EN-US%22%3E%3Cstrong%3EAbility to support the following%5C:%3C/strong%3E%3C/span%3E%3C/span%3E%3C/p%3E%3Cul style=%22margin-top%5C:0cm;%22 type=%22disc%22%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l2 level1 lfo2;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3ENetworking knowledge, TCP/IP suite knowledge, Linux%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l2 level1 lfo2;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EExperience writing Linux shell scripts or Python%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l2 level1 lfo2;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EExperience with Linux OS%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l2 level1 lfo2;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EExperience with integrated hardware-software products%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l2 level1 lfo2;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EFamiliarity with CPLD / FPGA / Board design%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l2 level1 lfo2;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EExcellent verbal and written communication skills%3C/span%3E%3C/span%3E%3C/li%3E%3C/ul%3E%3Cp class=%22MsoNormal%22 style=%22line-height%5C:150%;margin%5C:0cm 5.4pt;mso-layout-grid-align%5C:none;mso-pagination%5C:none;text-autospace%5C:none;%22%3E%26nbsp;%3C/p%3E%3Cp class=%22MsoNormal%22 style=%22line-height%5C:150%;margin%5C:0cm 5.4pt;mso-layout-grid-align%5C:none;mso-pagination%5C:none;text-autospace%5C:none;%22%3E%3Cspan style=%22color%5C:black;font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3E%3Cstrong%3EPersonal skills%5C:%3C/strong%3E%3C/span%3E%3C/span%3E%3C/p%3E%3Cul style=%22margin-top%5C:0cm;%22 type=%22disc%22%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l0 level1 lfo3;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EGreat human relations and self-motivated%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l0 level1 lfo3;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EAbility to work in a multitasking and dynamic environment%3C/span%3E%3C/span%3E%3C/li%3E%3Cli class=%22MsoNormal%22 style=%22color%5C:black;line-height%5C:150%;margin-bottom%5C:0cm;margin-right%5C:5.4pt;mso-layout-grid-align%5C:none;mso-list%5C:l0 level1 lfo3;mso-pagination%5C:none;tab-stops%5C:list 36.0pt;text-autospace%5C:none;%22%3E%3Cp%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan style=%22line-height%5C:150%;mso-ansi-language%5C:EN-US;mso-bidi-font-family%5C:%26quot;Century Gothic%26quot;;mso-font-kerning%5C:0pt;%22 lang=%22EN-US%22%3EAbility to quickly ramp up on and apply new technologies and processes%3C/span%3E%3C/span%3E%3C/p%3E%3Cp%3E%3Cbr%3E%3Cbr%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan lang=%22EN-US%22%3E%3Cstrong%3EWhy you should join us%5C:%3C/strong%3E%26nbsp;%3C/span%3E%3C/span%3E%3C/p%3E%3Cp%3E%26nbsp;%3C/p%3E%3Cp%3E%26nbsp;%3C/p%3E%3Cp class=%22MsoNormal%22%3E%3Cspan style=%22font-family%5C:Arial, Helvetica, sans-serif;font-size%5C:14px;%22%3E%3Cspan lang=%22EN-US%22%3EEmployees from more than 40 countries have chosen Radware as a place where they can belong.

Radware has been recognized by Glassdoor and BDI as one of the World’s Best Places to Work, ranking among the top 100 companies across the globe in the IT category. Radware has also been named a Gold Winner for Application Security in the 2023 Globee Cybersecurity Awards, by Forrester a Leader in DDoS Protection, and has been named a Leader in WAF Market by Quadrant Knowledge Solutions. We are equally committed to our people.

We strive to create a dynamic work environment that celebrates diversity, promotes equality, and thrives on the unique contributions of each individual. If you are ready to be part of a global-minded company that is inspired to create a better, safer future; and if and want to fight for the good guys and be at the forefront of helping companies protect their most critical assets from today’s cyber adversaries, then you’ve found the right fit at Radware.%3C/span%3E%3C/span%3E%3C/p%3E%3C/li%3E%3C/ul%3E