Staff CAD Layout Automation and Methodology Engineer

Job Summary:

The PDK team is looking for an experienced Staff CAD Physical Design Methodology Engineer based out of India region to enhance the team’s support for our business units.

Develop, integrate, maintain and deploy PDK Physical Design components/IP and methodologies for Analog, Mixed-Signal and Digital design teams across mature and advanced technology nodes.

Job Description:

• Develop, adapt, enhance and release PDK Physical Design flows and design enablement collateral for internal customers.
• Define and maintain physical-design methodologies, configurations and customization options for technology and product-specific requirements.
• Develop and maintain technology-dependent layout structures, reference components and supporting utilities.
• Translate foundry technology requirements into robust and reusable PDK Physical Design flows and solutions.
• Collaborate with foundries, EDA vendors, PDK and design teams to address physical-design requirements and integration.

• Good knowledge of CMOS , planar and finfet fundamentals, semiconductor technology and IC design, with a background in Electrical/Electronics Engineering, Semiconductor Physics or a related discipline.
• Strong understanding of IC physical design and layout methodologies, including technology-dependent layout requirements, chip-level integration and Tape-Out considerations.
• Demonstrable experience in  developing, integrating and maintaining  tools , flows for Physical design using Virtuoso environment
• Strong debugging and problem-solving skills across  layout, EDA and design-flow environments.
• Ability to interpret foundry technology documentation and design requirements and translate them into  flows using native EDA vendor tools or custom  tools
• Good knowledge of UNIX/Linux environments, shell scripting, with proficiency in Python, Perl
• Strong Cadence SKILL programming experience
• Experience developing automation and productivity tools for supporting design teams is highly desirable.
• Good communication and collaboration skills for working with foundries, EDA vendors, CAD/EDA teams and IC design teams.
• Background in Full chip layout/physical design development and Tapeout is highly desired

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.