As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
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To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
Role Summary
We are seeking a Senior Design Verification Engineer to own block‑ and subsystem‑level DV for advanced out‑of‑order (OoO) CPU cores. You will work closely with micro‑architects and RTL designers to verify complex execution pipelines, memory systems, and coherence protocols using modern, coverage‑driven methodologies.
Key Responsibilities
Verification Planning & Ownership
Drive verification for key OoO CPU blocks, such as:
Front‑end: fetch, branch prediction, decode.
Rename and register mapping.
Issue queues / schedulers and execution units.
Reorder buffer (ROB), retirement, exceptions, and flush/replay.
Load‑store unit (LSU), store buffer, atomics/LR‑SC, fences.
L1 caches, TLBs, MMU interfaces, and coherence interfaces.
Derive verification plans from architecture and micro‑architecture specs, with emphasis on:
Speculative execution flows and pipeline hazards.
Memory ordering / consistency model compliance.
Interaction with cache hierarchy and coherence.
Testbench & Environment Development
Develop and maintain SystemVerilog/UVM testbenches:
UVM agents, monitors, scoreboards, reference models.
Constrained‑random stimulus and directed tests for OoO corner cases.
Implement self‑checking mechanisms for:
Instruction retirement and architectural state.
LSU / memory ordering, atomics, and fence behavior.
TLB, page‑table, and privilege/protection flows as needed.
Coverage & Quality
Define and track functional, code, and assertion coverage; identify gaps and add tests/monitors to close them.
Create and maintain assertions (SVA) for key micro‑architectural properties:
No deadlock/livelock in scheduler, ROB, LSQ.
Correct handling of mispredicts, exceptions, interrupts, and flush paths.
Correct data forwarding and hazard resolution in the pipeline.
Analyze regression results, triage failures, and drive issues to closure with design and architecture teams.
Debug & Collaboration
Debug complex failures in:
Speculation / replay (e.g., wrong‑path side‑effects, partial flushes).
Load‑store ordering and memory consistency violations.
TLB / MMU corner cases and privilege/protection issues.
Collaborate with:
Micro‑architecture & RTL on fixes and design clarifications.
Performance / modeling teams to align micro‑architectural behavior and verification scenarios.
Post‑silicon / validation teams to correlate pre‑ and post‑silicon issues.
Methodology & Mentoring
Contribute to DV methodology improvements (UVM components, coverage strategies, regression flows).
Provide guidance and code reviews to junior engineers on testbench design, stimulus generation, and debug.
Required Qualifications
Education: BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Experience:
Typically 5–10 years of ASIC/SoC/IP design verification experience.
Direct experience verifying out‑of‑order or superscalar CPU cores (or closely related high‑performance pipelines).
Technical Skills:
Strong proficiency in System Verilog and UVM (or equivalent class‑based DV methodology).
Solid understanding of CPU micro‑architecture, including:
Fetch/decode, rename, ROB, issue/execute, bypassing, commit.
LSU, store buffer, atomics/LR‑SC, fences, and memory ordering.
L1 caches, TLBs, page‑table walkers, and basic coherence concepts.
Hands‑on experience with:
Constrained‑random and coverage‑driven verification.
Writing and debugging SVA assertions.
Industry‑standard simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).
Soft Skills:
Strong problem‑solving and debug skills on complex, corner‑case bugs.
Effective communication and teamwork across DV, design, and architecture.
Ability to work independently on complex blocks while contributing to a larger project.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Job details are sourced from the employer's original posting.
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As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.