Alternate Job Titles- Analog Circuit Design Engineer
- IO Design Engineer
- Mixed-Signal Design Engineer
- Analog IP Design Engineer
- Interface IP Design Engineer
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years designing analog and IO circuits that have to work across process corners, voltage swings, and temperature extremes, not just in simulation but in silicon. You know that the difference between a GPIO that meets spec and one that fails at the corner case is usually a design decision made during micro-architecture, and you are the kind of engineer who catches that before it gets to layout.
You are comfortable moving between IO standards like I3C, MIPI, SD-eMMC, and RFFE without losing sight of what you are actually building: circuits that need to be reliable, efficient, and manufacturable across nodes from 2nm GAA to 55nm bulk. Network analysis is not something you memorize, it is how you think. You can look at a schematic and see the second-order effects that matter.
You do not need a perfect spec to get started. You ask the right questions, sketch the topology, run the analysis, and iterate. Reliability is not a checkbox at the end, it is baked into how you design. At Synopsys, you will work on IO solutions that go into AI, automotive, HPC, and space applications with a team that cares about getting the physics right.
What You'll Be Doing
- Design and micro-architect analog and IO circuits from specifications, including GPIOs, I2C, I3C, SD-eMMC PHY, SPI, SPMI, RGMII, ONFI, RFFE, I2S, UART, and SMBUS blocks
- Develop circuit topologies that meet PPA targets across advanced technology nodes including sub-2nm GAA, GAE, FinFET, FDSOI, and bulk processes
- Perform detailed network analysis, transistor-level simulations, and corner analysis to validate design performance and reliability
- Conduct design reliability analysis including ESD, latch-up, aging, and stress testing to meet automotive, space, and industrial standards
- Collaborate with layout teams to ensure designs are optimized for area, parasitic effects, and manufacturability
- Work with foundry PDKs to ensure designs are aligned with process capabilities and constraints across all top foundries
- Drive continuous improvement in design methodologies to reduce turnaround time and improve design quality
The Impact You Will Have
- Deliver differentiated IO solutions that enable Synopsys customers to build next-generation AI, HPC, automotive, IoT, and space products
- Contribute to building a world-class IO design team that sets the standard for innovation and technical excellence at Synopsys
- Enable faster time-to-market for customers by delivering reliable, high-performance interface IP that integrates cleanly
- Push the boundaries of what is possible in advanced nodes by solving design challenges in GAA, GAE, and sub-2nm technologies
- Build design methodologies and best practices that scale across the IO IP team and improve overall design efficiency
- Support critical applications in space and automotive where reliability and robustness are non-negotiable
- Help establish Synopsys as the go-to provider for innovative IO solutions across the semiconductor industry
What You'll Need
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or equivalent technical field
- 2 to 6 years of hands-on experience in analog circuit design, IO design, or mixed-signal design
- Deep understanding of analog circuit design techniques including amplifiers, references, regulators, comparators, and interface circuits
- Strong grasp of semiconductor device physics and how transistor-level behavior impacts circuit performance across process nodes
- Proficiency in network analysis and ability to apply it to real-world circuit design problems
- Good grip on design reliability analysis including ESD, latch-up, aging, and stress effects
- Experience with circuit simulation tools such as HSPICE, Spectre, or similar SPICE-based environments
- Knowledge of IO standards such as I2C, I3C, SPI, UART, SD, MIPI, or similar protocols is a strong plus
Who You Are
- You can explain a design tradeoff between speed, power, and area in a design review without losing the technical nuance
- You are the kind of engineer who runs one more corner case because you know that is where the design will break if it is going to
- You do not treat layout as someone else's problem. You work with the team to make sure the design intent survives through GDS
- You are a strong team player who shares knowledge, reviews designs with peers, and learns from every tapeout
- You are focused on continuous learning and improvement, staying current with foundry roadmaps and new process technologies
- You communicate clearly and can translate complex circuit behavior into actionable insights for cross-functional teams
The Team You'll Be Part Of
You will join the IO Design team at Synopsys, a group focused on building differentiated and innovative IO solutions for AI, HPC, IoT, space, and automotive applications. The team designs a broad portfolio of interface IP including GPIOs, I2C, I3C, SD-eMMC PHY, SPI, SPMI, RGMII, ONFI, RFFE, I2S, UART, SMBUS, 3D IOs, and analog blocks across multiple advanced technology nodes ranging from sub-2nm to 55nm. You will work with cutting-edge process technologies including GAA, GAE, FinFET, FDSOI, and bulk, partnering with all top foundries. This is a team that values continuous learning, technical depth, and collaboration.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
