We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years designing analog circuits that move data at speeds where physics stops being forgiving and starts being the problem. You know that a high-speed link is not just about transistors, it is about package inductance, substrate coupling, jitter budgets, and the thirty other things that conspire to close an eye diagram at 32 Gbps. You have debugged enough silicon to know that the difference between a working PHY and a failing one often comes down to a decision you made six months earlier during floor planning or bias distribution.
You are comfortable moving between Spectre simulations, behavioral models in Python or MATLAB, and actual scope measurements in the lab. When a digital engineer asks why the receiver is not locking, you can explain it in terms they understand without losing the analog nuance. You do not need a perfect spec to get started. You work with what you have, build models to explore the tradeoffs, and align with signal integrity and packaging teams early because you have learned that waiting until tapeout is too late.
At Synopsys, you will design the analog PHY circuits that power UCIe die-to-die interfaces, the kind of IP that gets integrated into chiplets across the industry. The work is hard, the constraints are real, and what you build will ship.
What You'll Be Doing
- Define analog PHY architectures for UCIe and high-speed die-to-die interfaces, translating system requirements into circuit-level specifications for transmitters, receivers, equalization, clocking, and calibration blocks
- Design transistor-level analog and mixed-signal circuits including TX drivers, RX front-ends, continuous-time linear equalizers, decision feedback equalizers, delay-locked loops, bias generators, and termination circuits using Cadence Virtuoso, Spectre, Synopsys Custom Compiler, or HSPICE
- Build behavioral models for link performance analysis, jitter budgeting, BER estimation, and system-level trade-off exploration in collaboration with digital and signal integrity teams
- Verify designs across PVT corners, Monte Carlo mismatch, aging, reliability, and post-layout parasitic extraction, ensuring margin and performance targets are met before tapeout
- Analyze package, interposer, substrate, and channel effects including insertion loss, return loss, crosstalk, common-mode voltage, and eye closure, working closely with signal integrity and packaging engineers
- Support floor planning, layout reviews, parasitic back-annotation, and design sign-off, ensuring circuits meet area, power, and performance targets
- Lead silicon bring-up, lab characterization, compliance testing, and simulation-to-silicon correlation, debugging issues and driving root cause analysis with cross-functional teams
The Impact You Will Have
- Enable Synopsys to deliver UCIe PHY IP that powers the next generation of chiplet-based systems across AI, HPC, and data center applications
- Reduce time-to-market for customers by delivering analog circuits that meet first-pass silicon targets for BER, jitter, power, and eye performance
- Improve design quality and predictability by building accurate behavioral models and verification methodologies that catch issues before tapeout
- Strengthen collaboration between analog, digital, layout, signal integrity, and validation teams through clear communication and early alignment on critical design decisions
- Accelerate silicon debug cycles by correlating lab measurements to simulation, identifying root causes faster, and feeding learnings back into the design process
- Mentor junior engineers on analog design techniques, high-speed I/O fundamentals, and best practices for verification and silicon bring-up
- Contribute to technical reviews, design documentation, and IP release processes that ensure long-term maintainability and reuse across product lines
What You'll Need
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or equivalent practical experience
- 8 to 15 years of hands-on experience in analog or mixed-signal IC design, with a focus on high-speed interfaces
- Proven track record designing circuits for UCIe, die-to-die interconnects, SerDes, PCIe, Ethernet, CXL, USB, or similar high-speed I/O standards
- Deep expertise in analog circuit design including transmitters, receivers, equalization, DLLs, bias circuits, and high-speed drivers, with strong understanding of jitter, phase noise, linearity, signal integrity, and power trade-offs
- Strong proficiency with transistor-level design and simulation using Cadence Virtuoso/Spectre, Synopsys Custom Compiler/HSPICE, or equivalent tools
- Experience with schematic design, behavioral modeling, layout interaction, parasitic extraction, post-layout verification, and design sign-off in advanced semiconductor process nodes
- Hands-on experience with silicon bring-up, lab measurements using high-speed oscilloscopes and BERTs, debugging, and simulation-to-silicon correlation; familiarity with compliance testing and industry standards is a plus
Who You Are
- You can look at an eye diagram and know whether the problem is ISI, jitter, noise, or something in the package, and you know which knobs to turn to fix it
- You do not wait for the layout to come back to think about parasitics; you work with layout engineers during floor planning to minimize coupling, manage current return paths, and keep sensitive nodes clean
- You can explain a complex analog trade-off, like why increasing bias current does not always improve bandwidth, to a digital engineer or a project lead in two sentences without losing the nuance
- You are organized enough to manage multiple circuit blocks in parallel, track verification coverage across corners, and keep stakeholders aligned on schedule and risk
- You push back when a spec is unrealistic or a timeline does not account for the iteration cycles that analog design actually requires
- You have spent enough time in the lab to know that the scope does not lie, and you use that experience to build better models and make better decisions during design
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
