ASIC Digital Design, Staff Engineer- 16630

IP Prototyping Staff Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

Synopsys is seeking a creative and talented engineer to fill a FPGA Validation role in Bengaluru, India. The environment presents stimulating, challenging, and rewarding work within an excellent work environment with positive career development opportunities.

FPGA Design and Verification IP Prototyping team is responsible to build FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs and test them to verify their compliance with leading edge industry standards. We play a vital role on supporting Synopsys IP business by validating key features, and mitigating ASIC potential faults early on, in a prototype.

Responsibilities

• Design, implement, and verify FPGA-based systems for a variety of applications
• Validate FPGA-based IP prototype 'Device Under Test' against real-world devices, Test Equipment and other hardware systems
• Create and maintain comprehensive technical documentation
• Elaborate and execute test plans and test routines
• Detect, troubleshoot, debug, and investigate potential ASIC issues up front
• Establish and maintain relationships with cross-functional teams, internal and external customers

Key Qualifications

• Bachelor's or master's degree in electrical engineering
• 5+ years of experience in FPGA design and development
• Design and simulate integrated circuitry using Verilog, System Verilog
• Expertise with industry-standard scripting languages such Tcl, Python, Perl and Bash
• Expertise with industry-standard interfaces and protocols such as AMBA AXI or APB.
• Experience with FPGA development tools such as XILINX Vivado. Familiarity with Synopsys Synplify or Protocompiler is a plus
• Experience in digital design methods such as floor planning, timing constraints definition, and static timing analysis
• Excellent verbal and written communication skills in English

Preferred Experience

• Expertise with HAPS-100,HAPS-80 Boards and Protocompiler Flows
• Familiarity with peripheral interfaces like SD/eMMC and (LP)DDR
• Familiarity with simulation tools such as VCS
• Familiarity with laboratory equipment such as Oscilloscopes, Protocol-Analyzers

Travelling

• As a worldwide organization there is sometimes short term travel maybe required.

The Team You’ll Be a Part Of:

You will be joining the FPGA Design and Verification IP Prototyping team, a group of innovative engineers dedicated to building FPGA-based hardware prototypes of Synopsys Controllers and PHY Interface IPs. The team plays a pivotal role in supporting Synopsys' IP business by validating key features, mitigating ASIC potential faults early, and ensuring compliance with industry standards. Collaboration and continuous learning are at the heart of the team, offering a stimulating, challenging, and rewarding environment with positive career development opportunities.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.