ASIC Digital Verification, Principal Engineer 18720

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

An experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement.

What You’ll Be Doing:

• Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
• Creating and executing detailed test plans to verify complex ASIC designs.
• Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.
• Collaborating with design and architecture teams to identify and fix bugs.
• Performing functional coverage analysis and driving coverage closure.
• Mentoring and guiding junior verification engineers in best practices and methodologies.

The Impact You Will Have:

• Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.
• Enhancing the robustness and efficiency of our verification processes and methodologies.
• Contributing to the successful launch of Interface IP products, impacting various industries.
• Driving innovation and excellence within the verification team.
• Improving the overall performance and functionality of Synopsys' IP offerings.
• Fostering a culture of continuous improvement and technical excellence.

What You’ll Need:

• Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as DDR, PCIe, CXL, Ethernet.
• Proficiency in SystemVerilog and UVM methodologies.
• Strong understanding of digital design and verification concepts.
• Experience with simulation tools such as VCS, ModelSim, or similar.
• Excellent problem-solving skills and attention to detail.

Who You Are:

• Detail-oriented with a strong analytical mindset.
• Excellent communicator, able to convey complex technical concepts clearly.
• Collaborative team player who thrives in a dynamic environment.
• Proactive and self-motivated, with a commitment to continuous learning.
• Mentor and leader, capable of guiding and developing junior engineers.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on advancing Synopsys' design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry. Specifically, you will be a key technical contributor to the architecture and execution of one of DDR controller digital core products.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.