We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent a decade or more working at the boundary between semiconductor technology and the people who need to make it real. You understand that the hardest part of bringing up IP on a new process node is not the design itself, it is the coordination across foundries, R&D teams, and customers who all speak slightly different technical languages and operate on conflicting timelines. You know how to translate a foundry's PDK release schedule into an actionable internal roadmap, and you can spot a brewing integration issue three months before it derails a tapeout.
You are comfortable sitting in a meeting with foundry engineers in Hsinchu discussing FinFET design rule updates, then turning around and briefing your VP on what that means for next quarter's IP portfolio. You do not wait for someone else to connect the dots. When a test chip fails characterization or a process migration hits a snag, you are the one who pulls the right people into the room, frames the problem clearly, and drives it to closure without drama.
You have a point of view on what good partner engagement looks like, and you push back when communication plans are too vague or escalation paths are missing. At Synopsys, you will work with the world's leading foundries on the most advanced process technologies, and the programs you run will directly enable the IP that powers the next generation of AI, automotive, and mobile SoCs.
What You'll Be Doing
- Serve as the primary interface between Synopsys and foundry partners in Taiwan, coordinating IP enablement programs across multiple process nodes and technology platforms
- Manage cross-functional communication between Sales, Marketing, FAE, CAE, R&D, and foundry engineering teams to align on schedules, deliverables, and technical requirements
- Track and drive resolution of technical issues related to PDK updates, design kit releases, IP characterization, and test chip bring-up
- Identify program risks early, escalate appropriately, and coordinate mitigation plans across internal and external stakeholders
- Coordinate test chip design, tapeout schedules, and silicon characterization activities with foundry partners to validate IP performance on new process technologies
- Maintain program dashboards, status reports, and executive briefings that translate complex technical progress into clear business outcomes
- Bridge foundry adoption timelines with internal IP development roadmaps, ensuring Synopsys IP is ready when customers need it for their SoC designs
The Impact You Will Have
- Enable Synopsys IP to be available on leading-edge process nodes faster, giving customers earlier access to differentiated IP for their products
- Reduce time-to-market for customer SoCs by ensuring smooth IP integration and fewer late-stage surprises during tapeout
- Strengthen foundry partnerships by being the reliable, knowledgeable point of contact who makes collaboration easier and more predictable
- Improve internal R&D efficiency by surfacing foundry updates and design kit changes before they become blockers
- Drive higher IP quality and performance by coordinating thorough test chip validation and silicon characterization programs
- Increase customer confidence in Synopsys IP by ensuring robust enablement and proven silicon results on the processes they care about
- Shape how Synopsys engages with foundries on future technology nodes by bringing lessons learned and process improvements back into the organization
What You'll Need
- Bachelor's degree in Electrical Engineering or equivalent technical field with 10 to 15+ years of relevant semiconductor industry experience
- Deep working knowledge of IC manufacturing, process technology nodes, design enablement flows, and sign-off processes
- Fluency in both English and Mandarin, with the ability to navigate technical discussions and business negotiations in both languages
- Direct experience coordinating with foundries, whether through PDK development, IP design, CAD tool enablement, or quality management programs
- Familiarity with analog and digital SoC design flows, including physical design, characterization, and silicon validation methodologies
- Proficiency in Microsoft Office tools for program tracking and reporting; working knowledge of Copilot is a plus
- Experience communicating technical program status to stakeholders at multiple levels, from engineering teams to executive leadership
Who You Are
- You can walk into a technical review with foundry engineers, absorb the details of a new design rule change, and walk out with a clear plan for how it affects your IP roadmap
- You do not need perfect information to move forward, you work with what you have, ask the right questions, and fill in the gaps as you go
- You are organized enough to manage five concurrent process node programs without losing track of critical milestones, and you know when to escalate before a slip becomes a crisis
- You can explain a complex PDK compatibility issue to a sales leader in two sentences without losing the technical nuance that matters
- You build relationships that last, foundry partners and internal teams trust you because you follow through and you do not overpromise
- You have a strong sense of priority and you push back when a request does not align with the program's real goals or timeline constraints
