CPU Core Design Verification Test Generator Lead

At Tenstorrent, we build open, state of the art compute for real workloads and real developers.

You will own CPU focused test generator development and verification strategy, shaping how our out-of-order RISC-V CPUs are validated against complex ISA and microarchitectural behavior.

This role is hybrid, based out of Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are 

• You bring 8+ years in CPU design verification, test generation, or closely related CPU validation work.
• You have led development of test generators for x86, ARM, or RISC-V ISA environments.
• You understand CPU ISA behavior, privileged architecture, and high-performance out-of-order CPU microarchitecture.
• You are comfortable building tools, stimulus, and automation that scale verification across large CPU programs.
• You communicate clearly across design, DV, architecture, emulation, and post-silicon teams.

What We Need 

• Lead development of CPU core-level test generators for high-performance out-of-order RISC-V cores.
• Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification in both pre-silicon and post-silicon
• Develop directed and randomized stimulus that targets architectural corner cases, instruction interactions, and complex CPU behavior.
• Support RISC-V certification work, including test content, compliance flows, debug, and closure.
• Guide a small team of 4-5 engineers while staying hands-on with implementation, debug, and verification execution.

What You Will Learn 

• How Tenstorrent designs and validates high-performance RISC-V CPU cores and clusters.
• Techniques for scaling CPU test generator infrastructure across core, cluster, and chip-level environments.
• Ways to apply ISA-driven stimulus to complex CPU verification and debug workflows.
• Techniques for supporting RISC-V certification alongside internal verification requirements.
• How to scale coverage, debug, and generator methodology across multiple CPU programs within Tenstorrent’s broader compute roadmap.